Agnisys Delivers Fully Automated, Specification-Based Design and Verification Flow for Registers and Sequences - FirstEDA
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Agnisys Delivers Fully Automated, Specification-Based Design and Verification Flow for Registers and Sequences

Three new products generate IP, assemble complete chips, and provide a common front end for SoC automation

 

Agnisys, Inc., the leading EDA provider of the industry’s most comprehensive solution for Design and Verification of SoC Hardware/Software Interface (HSI), today announced general availability of three major new products: SLIP-G, SoC Enterprise and IDS NextGen (IDS-NG). When combined with existing products, Agnisys now delivers a complete flow from register and sequence specification to assembly, design, verification, and validation of complex system-on-chip (SoC) devices.

 

Standard Library of IP Generators (SLIP-G) provides an interface for IP customization and configuration, and generates the IP register-transfer-level (RTL) design, testbench models compliant with the Universal Verification Methodology (UVM), and programming sequences. GPIO, I2C, timer, and programmable interrupt controller (PIC) IP is available today, with additional titles in the future based on customer demand.