Henderson, NV – November 16, 2021 – Aldec, Inc., a pioneer in mixed HDL language simulation and hardware-assisted verification for FPGA, ASIC and SoC designs, has added an automatic UVM Generator function to Riviera-PRO.
The addition promises to greatly boost the productivity of Riviera-PRO users taking advantage of the benefits of the Universal Verification Methodology, which contains guidance on the creation and reuse of verification testbenches…