VHDL for FPGA Designers – 25-27 February 2025

Remote Live Session

Instructor Led Online Training

 

This instructor-led online training course provides a thorough background in the use and application of synthesisable VHDL in digital hardware design.

 

 

The online training is structured around a set of basic component building blocks to demonstrate the application of VHDL.

This is the first part of our VHDL online training series, covering basic concepts and syntax relating to the circuit structures covered, and gives the FPGA designer sufficient knowledge to start writing synthesisable VHDL upon successful completion of the course. We also provide additional VHDL training classes which cover the more advanced language constructs and methodologies.

Online courses include daily live interactive group lecture sessions, with our instructors. Training materials and software licenses are provided in advance, to allow delegates to complete lab exercises between lecture time. Realtime one-on-one support and guidance from the trainer is available throughout.

Course benefits:

  • To provide a complete understanding of the basic concepts in VHDL
  • To introduce you to the syntax and language building blocks based on a number of common circuit elements
  • To give you practical experience of writing and verifying simple VHDL designs

 

The course includes a number of labs, designed to develop logically during the training. Each delegate is given a high quality colour printed training notebook containing all the material covered during the course. This notebook will prove an invaluable resource as you start your HDL design journey. Each delegate will also be provided with a high quality colour printed A5 lab workbook, the files they created during the training, the solutions for the lab exercises as well as a useful library of basic VHDL components to enable delegates to expand their knowledge once they have left the classroom.

Delegates should have a basic knowledge of using a PC running the Microsoft Windows operating system. The course assumes no prior knowledge of VHDL but experience of other software languages would be useful (but not essential).

Use this form to request further information, availability or pricing details.

 

Please note, by submitting this form you are not reserving a place on the course. In order to book a place, you will need to speak with a member of our training team.

Training Terms and Conditions.

FirstEDA Training

“VHDL for FPGA Designers is a brilliant course for engineers wanting to use VHDL for the first time. Lab exercises were particularly valuable. The trainer explained concepts well and was happy to answer questions.”

– Abdul Qadir Syed – A Q Electronix

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