PR: DVCon Europe “must see”

DVCon Europe “must see”: Aldec tutorial and demonstration on adopting Easier UVM to enable FPGA-based Acceleration

Aldec, Inc., a pioneer in mixed HDL language simulation and hardware-assisted verification solutions for system and ASIC designs, is supporting the second Annual DVCon Europe conference taking place in Munich on Nov 11th and 12th. Not only have Aldec been chosen to present a technical tutorial on UVM acceleration but they are also showing live demonstrations at the conference exhibition of hardware-assisted verification of UVM following Doulos Ltd.’s Easier UVM guidelines. John Aynsley, Chief Technology Officer of Doulos and pioneer of the UVM standard, says “I am happy that Aldec endorses our Easier UVM approach as an excellent starting point and learning aid.”

 

The 90-minute tutorial focusses on the use of Easier UVM and SCE-MI to help teams get started with UVM and, importantly, to future-proof their UVM verification environments by making them acceleration-ready right from the start. Given the growth of FPGA-based emulation, simulation acceleration is becoming widely adopted, so the tutorial is timely in explaining that by being ready for acceleration, even late adopters of UVM can be early for the next wave of mainstream emulation.

 

Aldec verification expert, Alex Grove will give a real-world example of the use of Easier UVM, following on from an introduction by Doulos earlier in the DVCon conference. “Many verification teams may be familiar with the potential benefits of FPGA-based Verification” says Grove, “however, there is little material on how to harness FPGAs into mainstream verification methodology such as UVM; our tutorial aims to fill that gap”. Krzysztof “Chris” Szczur, co-author of the tutorial adds “in the tutorial, Alex will explain a UVM test environment that is acceleration-ready through the use of the Accellera SCE-MI standard and Easier UVM. Delegates will learn how this approach allows tests to be run in simulation and then accelerated on an FPGA Co-emulator through use of Aldec’s SCE-MI compiler.”