Blog: Constrained random testing – the magic bullet?

OSVVM provides a low-risk approach to improving verification effectiveness when adopted as part of a cohesive methodology
—

Change can be a double edged sword; it drives us to learn (which is great!) but as things develop and we adapt our methods, we must not forget how we worked in the past. Sometimes it appears as if change is forced just for the sake of it and consequently important lessons are often lost or overlooked.

One ever changing constant (and throughout the many years since I started working in FPGA design and verification) is the steady increase in device size and resultant complexity. This brings with it many challenges, not least those associated with verification. Originally we exclusively used directed test to verify that our designs functioned as intended but, as designs grew ever larger, the verification effort exploded. For a modern design it’s not unreasonable to expect that 75% of development time be committed to verification. A new approach was required and constrained random verification (CRV) seemed to be the way to go. With this methodology, the engineer does not have to write many individual test cases, as a small set of constrained-random scenarios can be good enough to fulfil our coverage goals (functional as well as code coverage). Or at least that was the promise…

It is fair to say that CRV is not the answer to all our device test requirements; there are certain aspects where it falls short. Because of this I have seen an increasing number of our customers returning to a directed test approach but now mixing with constrained random verification and functional coverage. For many FPGA engineers in Europe, designing and verifying with VHDL, such verification strategies may seem overly complex (into the realms of SystemVerilog and UVM with associated steep learning curves and increased tooling cost) but this isn’t necessarily the case. By using the freely available packages provided in Open Source VHDL Verification Methodology (OSVVM), anyone can add constrained random verification to their VHDL verification arsenal.

OSVVM is an intelligent testbench methodology that allows mixing of ‘Intelligent Coverage’ (coverage driven randomisation) with directed, algorithmic, file based and constrained random test approaches. The methodology can be adopted in part or in whole as needed, so you don’t need to fully deploy a new verification approach; you can mix and apply it to your current activities. With OSVVM you can add advanced verification methodologies to your current testbench without having to learn a new language or throw out your existing testbench code and models.

OSVVM is based on a set of open source (free) packages:

• CoveragePkg for functional coverage and “Intelligent Coverage”
• RandomPkg for constrained random (CR) utilities.
• AlertLogPkg to record what happened and when.

FirstEDA work closely with the founders of OSVVM and in partnership with the methodology’s Chief Architect, Jim Lewis, to deliver an advanced verification workshop developed specifically for VHDL designers. Here you will learn not just about constrained random verification in VHDL, but also how easy it is to mix this with directed test, to ensure you are using the best techniques to verify the functionality of your design. Jim Lewis has 30 years of design and teaching experience and, as well as being the driving force behind the OSVVM methodology, is the Chair of the VHDL Standards Working Group at the IEEE. You would be hard pressed to find a more qualified instructor!

Like other verification languages, it is all about methodology but because it’s in VHDL (the language you are already familiar with) you can use it to enhance your current verification approach, rather than having to replace it.

There is a wealth of information available online regarding OSVVM. The OSVVM website and forum can be found at www.osvvm.org. Here you can download the packages and discuss the methodology with other like-minded engineers. Aldec have been a supporter of the OSVVM methodology since its inception and there are various white papers and recorded webinars that can be accessed through their website too (www.aldec.com/en/downloads).

Our next 5-day Advanced Verification workshops (and the last public ones of 2015!) are taking place in September (Bracknell, UK) and November (Copenhagen, Denmark).