These days, verification of the most complex designs is performed using a standard verification methodology, probably SystemVerilog-based UVM. Many verification teams have ramped up on UVM, but others have yet to take the plunge. Why is that? And how big a “plunge” is it, anyway?
If UVM is as great as all that, then why hasn’t everybody adopted it already? Is it not as “Universal” as we first thought, or are there barriers to its adoption? If so, what might these barriers be and how can they be overcome?