Live Webinar: The elusive systemic error – equivalence checking for your FPGA

Alex Grove

FirstEDA

Discover why designs teams are increasingly seeing the value of running equivalence checking during FPGA development to rapidly detect flow integrity issues and pinpoint the root cause
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WEDNESDAY 1 JULY – 14:00-15:00 BST (15:00-16:00 CEST)
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So, you are in the lab on schedule – great! However, there is a problem with bring-up and the pressure is on. A lack of confidence in the design may lead us to immediately start debugging the design functionality. In fact, the first question we should ask ourselves is, “could this be a systemic error?”

Systemic errors are often difficult to detect; at best found in the lab and very challenging to debug. The use of Equivalence Checking (EC) allows a design team to prove exhaustively that the FPGA implementation is equivalent to the RTL design description. EC is becoming an important capability in the verification of designs in safety critical and high reliability applications.

In this webinar we discuss the benefits of EC for FPGA programmes, propose design guidelines for EC, and run a Q&A session after the presentation.