The training is structured around a set of basic component building blocks to demonstrate the application of VHDL.
This is the first part of our VHDL training series, covering basic concepts and syntax relating to the circuit structures covered, and gives the FPGA designer sufficient knowledge to start writing synthesisable VHDL upon successful completion of the course. We also provide additional VHDL training classes which cover the more advanced language constructs and methodologies.
Abdul Qadir Syed - A Q Electronix
David Brunton - Ultra Electronics CIS