FPGA Design & Verification in Active-HDL - FirstEDA
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FPGA Design & Verification in Active-HDL


This internally developed training provides a basic understanding of all the design entry methods within Active-HDL (HDL code, Block Diagram & Finite State Machine). The flow then continues, using the design files created, to progress through the simulation and debug environment.

Whether you are currently using Active-HDL, or considering purchasing, this course is a must, and will teach you all you need to know for your day-to-day FPGA design, verification, analysis and documentation tasks.


  • To provide a complete understanding of the basic concepts of Active-HDL
  • To introduce you to the tools and methodologies within Active-HDL
  • To give you practical experience of applying the tools and methodology on simple HDL designs

Course labs will familiarise you with Active-HDL, building on the knowledge learned during the lecture sessions. The lab workbook provides step-by-step instructions to guide you through every stage of using the tools; design entry, simulation, analysis and documentation. Delegates are not required to have prior knowledge of Aldec Active-HDL but experience of VHDL or other FPGA design software is useful (but not essential).