ASSERTION-BASED VERIFICATION / FPGA / FV / SAFETY / ASIC
360 DV-Verify is a unified coverage-driven assertion-based verification solution. The combination of a fully functional, high-performance formal property analyser with a unique assertion coverage evaluator eliminates the guesswork from quality assertion generation.
DV-Verify is designed to augment existing verification environments, enabling the discovery of bugs which are hard to find in simulation-only environments, while maximising coverage.
The tool includes OneSpin’s unique Quantify MDV technology, which evaluates the effectiveness of assertion sets at tracking structural design issues. This “Observation Coverage” approach to understanding verification quality provides the clearest achieved coverage metrics, as well as giving you visibility into “dead code” and other potential issues.
DV-Verify also includes pre-packaged solutions (or “apps”) for off-the-shelf verification or as convenient assertion templates. These are: Protocol Compliance, Connectivity Checking, Register Map Verification, Formal Score-boarding and X-Propagation Analysis.
FIRST AND FOREMOST
Provides a Metric Driven Verification Solution through a set of applications that target the verification of RTL IP blocks, and the integration into a System-on-Chip (SoC).
- Integrates easily into an existing design flow
- VHDL, Verilog and SystemVerilog supported
- SVA, PSL and OVL are supported
- Ease of set-up
- Advanced debugging tools including a structural assertion debugger, waveform debugging and source code analysis
- The ability to compile with standard RTL behaviour or without X-Optimisation
- Formal coverage analysis for metric-driven assertion-based verification
- Share computationally heavy tasks over a network