GateVision PRO - FirstEDA
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GateVision PRO

gate-level netlist viewing & debugging / FPGA / ASIC

GateVision PRO is a graphical gate-level netlist analyser and netlist viewer. It provides designers working on even the largest ICs and SoCs with intuitive design navigation, netlist viewing, waveform viewing, logic cone extraction, interactive logic cone viewing for netlist debugging and design documentation.


GateVision PRO is a fast gate-level netlist viewing and debugging tool that fits seamlessly into any design environment. GateVision PRO is capable of handling extremely large Verilog, EDIF and LEF/DEF netlists. Schematics are generated on the fly and the intuitive GUI allows the designer to incrementally and very easily navigate through the largest netlist files.

  • Ultra-fast netlist readers – Netlist to schematics on the fly (within seconds)
  • 32/64-bit database – Higher performance and increased capacity, for very large designs
  • Integrated waveform viewer – For easy signal tracing and simulation results analysis (accelerated VCD viewer)
  • Automatic clock tree and clock domain extraction and visualisation – Faster detection and resolution for clock domain problems
  • Con Window – incremental schematic navigation for big designs
  • Verilog Netlist Export – Fragments of a circuit can be saved as Verilog netlist files
  • Tcl UserWare API – Allows interfacing with tool flow and definition of electrical rule checks
  • Netlist to schematics – Verilog viewer, EDIF viewer, and LEF/DEF viewer in one tool allows debugging of almost any netlist file format
  • Powerful GUI – Multiple views, including tree, schematic, waveform, cone and source file for increased circuit understanding plus drag-and-drop between different views
  • Automatic path extraction – Automatically extracts logic cones from user-defined reference points and shows only the relevant portion of the circuit. This reduces complexity in the design for improved and faster netlist debugging
  • Search-and-show capability – Easy location of specific objects shortens debug time
  • Design hierarchy browser – Provides easy navigation through the design hierarchy and gives compact hierarchy overview
  • Object cross-probing – Highlights selected objects in all design views (schematic, logic cone and HDL source code view) and shortens debug time
  • Context-sensitive menus – Easy-to-use GUI
GateVision PRO is the third generation of graphical netlist analysers from Concept Engineering. FirstEDA have been representing GateVision PRO for over 10 years.