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Clock Domain Crossing Verification / FPGA / FV / SAFETY / ASIC

ALINT-PRO-CDC is a design verification solution focused on asynchronous clock domain crossing analysis and used to manage metastability in designs with multiple clock domains.

ALINT-PRO-CDC focuses on three key areas of CDC Verification, statically pointing out clock and reset network connection problems as well as synchronisation circuit drawbacks. Design constraints setup is facilitated by automatic generation of an SDC file, providing a starting point for the design configuration. Dynamic functional verification is based on integration with Riviera-PRO through automatically generated SystemVerilog testbenches.


ALINT-PRO-CDC features an intuitive framework, which offers rich means for efficient design analysis including schematic viewer, clocks and resets viewer and elaboration viewer.


ALINT-PRO-CDC provides a set of capabilities for the analysis of CDC paths in a programmable design so to aid the review of such logic. Design rule checks are available for common CDC protocol requirements that can be checked both statically and dynamically through the use of auto generated assertions in simulation.

  • Structural verification with design rule checking for common CDC protocols
  • Clock and reset network analysis
  • Schematic viewer
  • SDC support
  • Design constraints extension for IP description
  • Metastability insertion
The cost of a CDC issue in the field can be expensive in terms of both time to resolve and customer satisfaction. Using ALINT-PRO-CDC our customers have been able to mitigate the risk of CDC issues in their production use of programmable devices.