Intermediate VHDL — 26-28 February 2019 — Bracknell, UK - FirstEDA
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Intermediate VHDL — 26-28 February 2019 — Bracknell, UK


Ready for the next step? For those already familiar with VHDL (either through an introductory course or self-taught), this workshop will broaden knowledge and enforce competency through application.

This instructor-led workshop was designed to bridge the gap between possessing a basic working knowledge of VHDL and our Advanced VHDL Verification & Testbenches course. All our courses are delivered by time-served engineers whose experiences go far beyond just the theory.


  • To provide practical experience in writing, testing and synthesising VHDL code as well as how to implement it on an FPGA
  • To enhance your current understanding of VHDL through problematic hardware coding issues
  • To introduce you to transaction-based testbenches
  • To introduce FSM coding techniques
  • To provide VHDL hardware experience with an FPGA lab board

The course is split (roughly 50/50) between lecture and lab time, so there is plenty of opportunity to reinforce the theory.


Delegates will be provided with a high quality lecture book and a detailed lab book (supporting all of the material covered during the course). Each delegate will also be provided with an FPGA development board which is used during the lab exercises and can be used after the course to further expand their VHDL knowledge.


Delegates should be familiar with digital design and have a basic understanding of VHDL. Although not essential, an understanding of other HDL or programming languages would also be useful.
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