Article: Chip Design Verification: It’s All About the Coverage - FirstEDA
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Article: Chip Design Verification: It’s All About the Coverage

By Tom Anderson (Contributed Content) | 2 January 2019

 

As the cost of chip turns has grown from thousands to millions of dollars, missed design bugs are unacceptable.

 

Chip design verification used to be straightforward, if not always easy. Verification engineers (sometimes designers playing a double role) created a spreadsheet of all of the design features and then wrote a test to verify each one. As tests were written and passed in simulation, the features were checked off on the spreadsheet, which served as a de facto verification plan. When all of the tests were passing, verification was declared complete, and the chip was released to place-and-route and — eventually — taped out.