You will gain the knowledge needed to improve your verification productivity and create a VHDL testbench environment that is competitive with other verification languages, such as SystemVerilog (UVM).
Unlike UVM, our methodology works with any simulator that supports VHDL-2008, removing the requirement to learn a new language or invest in new and costly tools.
Developed and delivered by Jim Lewis, chair of the IEEE VHDL standards working group and chief architect of OSVVM.
To ensure in-depth learning, 50% of the class time is devoted to hands on exercises and labs. The lecture and labs contain numerous examples that can be used as templates to accelerate your test and testbench development.
Delegates should have a good working knowledge of digital circuits and prior exposure to VHDL, either through work or through a previous course.