Advanced VHDL Testbenches & Verification — 12-16 November 2018 - FirstEDA
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Advanced VHDL Testbenches & Verification — 12-16 November 2018


Developed and delivered in person by VHDL specialist Jim Lewis, this is ideal for device (PLD/FPGA/ASIC) designers who are looking to improve their verification skills.

Jim Lewis has almost 30 years of design and teaching experience. He is a founding member of the Open Source VHDL Verification Methodology (OSVVM), the principle architect of its packages and methodology, and Chair of the VHDL Standards Working Group at IEEE. You would be hard pressed to find a more qualified instructor.   During the course you will learn advanced VHDL coding styles, techniques and methodologies that will ensure you become more productive at design verification and testbenches.

Core topics include transaction level modelling (TLM), data structures (linked-lists, scoreboards, memories), test generation methods (directed, algorithmic, constrained random and intelligent testbench), self-checking and functional coverage.


  • Improve design verification and testbench productivity
  • Learn how to create a transaction-based, system-level, self-checking test environment
  • Implement interface functionality with either a sub-program or bus functional model (aka transaction-level model or TLM)
  • Use sub-programs to abstract interface actions (CpuRead, CpuWrite, UartSend)
  • Write directed, algorithmic, constrained random, coverage driven random tests or a mixture of them
  • Write a test plan that maximises reuse from RTL to core to system-level tests
  • Reuse SynthWorks’ packages for constrained random testing, functional coverage, memories, scoreboards and interfaces
  • Model interface behaviour with proper timing
  • Model analogue values and periodic waveforms
  • Use VHDL’s file read and write capabilities effectively

The course is split (roughly 50/50) between lecture and lab time, so there is plenty of opportunity to reinforce the theory. Each delegate will be provided with access to a laptop, Aldec Riviera-PRO and all the necessary resources required.
Delegates should have a good working knowledge of digital circuits and prior exposure to VHDL, either through work or through a previous course.
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